ASSEMBLOR 8086 Saut conditionel inferieur JB (jump bellow) superior JA (jump above) Saut inconditionnel jmp short .. jmp jmp far jmp cx jmp memory disable any interrupt: pushf CLI restore it popf enable it sti before using string manipulation (stosw ..) cld -> increment new feature in 80186: PUSH cte <- mov ax,cte push ax shift/rotate al,Count <- mov cl,cte shift/rotate cl PUSHA POPA ENTER register r/m reg w=1 (16 bit) w=0 (8 bit) 000 ax al 001 cx cl 010 dx dl 011 bx bl 100 sp ah 101 bp ch 110 si dh 111 di bh Set of instruction: =================== data transfer: 8086 MOV PUSH POP XCHG IN OUT LAHF SAHF PUSHF POPF arithmetic: 8086 ADD ADC INC SUB SBB DEC CMP NEG AAA DAA AAS DAS MUL IMUL DIV IDIV AAM AAD CBW CWD logic: 8086 ROL ROR RCL RCR SHL/SAL SHR SAR AND TEST OR XOR NOT control transfer: 8086 CALL JMP RET Jcond LOOP INT IRET 80186 ENTER LEAVE BOUND Clock time of current instruction ================================= LEAVE timing: to have time: clock cycle * clock period ex: clock period=40ns for 25Mhz 486 -notation: true,false -n=number of repitition -m=number of components of the next instruction: m=1 for the instruction and prefixes and other bit m++ if access to imediate data m++ if displacement -pm=when it's in protected mode * add one if offset requires summing 3 elements ex: mov r,r/m 2,3* if r/m=r 2 if r/m=m 3 8086 80186 see p 3-39 User Manual All of the instruction times given are of the form n(m) wher n is the number of clock requires for 8086 and m for 80186 For instruction which repeat a specified number of times values of n & m consists of two parts in the relation x +y/rep x is the initial number of clock required and y is the number corresponding to the number of repitition specified 286 if two clock counts are given the smallers refers to a register operand, the second to a memory operand 386 * Misaligned or 32 bit operand: add 2 clock 486 true,false for reg/for memory true/false time: 8086 80186 80286 386-SX|DX 486-SX,DX,DX2 8-16bit data transfer R Pm R Pm mov r/m,reg 2/9+EA 2/9+EA 2/3* 2/2 1 mov reg,r/m 2/8+EA 2/12+EA 2/5* 2/4 1 mov r/m,cte 4/10 3-4/12-13 2/3* 2/2 1 mov ax,mem 10 8 5 4* 1 mov mem,ax 10 9 3 2* 1 push r/m 11/16+EA 10/16+EA 3/5* 2/7* 4/9*|5 1 push cte ** 10 3 2 4|2 1 pop r/m 8/17+EA 10/20+EA 5/5* 5/7 6/9|5 1 xchg ax,reg 3 3 3 3 3 xchg reg,r/m 4/17+EA 4/17+EA 3/5* 3/5 3/5 in al,cte 10 10 5 12* 6* 14 9 in al,dx 8 8 5 13* 7* 14 8 out cte,al 10 9 3 10* 4* 16 11 out dx,al 8 7 3 11* 5* 16 10 arithmetic: +/- reg,reg 3 3 2 2 1 +/- r/m,cte 4/17+EA 4/16+EA 3/7* 2/7** 1 mul al,r/m 70/76+EA 26/32+EA 13/16 12/15 13/13 mul ax,r/m 118/124+EA 35/41+EA 21/24 12/25 13/13 div al,r/m 80/86+EA 29/35+EA 14/17 14/17 16/16 div ax,r/m 144/154+EA 38/44+EA 22/25 22/25 24/24 inc/dec r/m 3/15+EA 3/15+EA 2/7* 2/6** 1 cmp reg,reg 3 2 cmp r/m,cte 4/10+EA 3-4/10+EA 3/6* 2/5* 1 logic: sal,sar rol,ror shl,shr r/m,1 2/15+EA 2/15+EA 3/7* 3/7** 2/4 test mem,cte 4/11+EA 3-4/10+EA 2/6* 2 1 and or xor reg,r/m 3/17+EA 3/16+EA 2/7* 2 1 control transfer: jmp short 15 14 7+m 7+m 3 jccc 16 or 4 13 or 4 7+m or 3 7+m or 3 3 or 1 loop 17 or 5 15 or 5 8+m or 4 11+m 7 or 6 loopcc 18 or 6 16 or 6 8+m or 4 11+m 9 or 6 Preference: CPU fast version slower or equivalent .---------------------------.-----------------------. |? |les di,4[bp]|mov di,4 (?) | | | |mov es,_STACK (?) | |---------------------------.-----------------------| |? |les di,cs:va|mov di,OFFSET va | | | |mov es,OFFSET va+2| |---------------------------.-----------------------| |all |add sp,2 | pop dummy | |-----------+---------------+-----------------------| |all |mov ah,al | xchg al,ah | |-----------+---------------+-----------------------| |all |xor ax,ax | mov ax,0 | |-----------+---------------+-----------------------| |all |test ax,mask | cmp ax,mask | |-----------+---------------+-----------------------| |all |sub ax,2 | dec ax | | | | dec ax | |-----------+---------------+-----------------------| |8086-286 |loop toto | dec cx | | | | jnz toto | |-----------+---------------+-----------------------| |8086-286 |shl ax,1 | add ax,ax | |-----------+---------------+-----------------------| |80386-486 |add ax,ax | shl ax,1 | |-----------+---------------+-----------------------| |80386-486 |dec cx | loop toto | | |jnz toto | | `-----------"---------------"-----------------------' structure d'un programme title mon_programme ASSUME cs:cseg,ds:dseg,es:NOTHING segment data ------------ dseg segment public 'data' .. toto db 'gkdsfjglkjdsfl' .. dseg ENDS cseg segment public 'code' or _TEXT segment public 'code' xor al,al faster than mov al,0 procedure: ---------- myproc proc near .. ... .. myproc endp cseg ENDS END Directive: ---------- macro ----- equate: constant equ es:4[di+tuu] tempo = 4[bp] tempo = 6[bp] real macro ========== General form: ------------- my_macro MACRO ARGUMENT1,ARGUMENT2.. body endm Specific operator in macro: --------------------------- & Substitute Operator <> Literal-text Operator ! Literal-character Operator % Expression in operator ;; Macro comment (not visible in the listing) A) IRP parameter,<argument[,argument]> statements endm ;test with IRP irp xx,<'a','b','c'> ;;xx is a variable ;;<> is necessary db 'Hello xx',xx endm is expanded as 0000: 61 78 78 db a , xx 0003: 62 78 78 db b , xx 0006: 63 78 78 db c , xx ; irp yy ; db 'no argument' ; endm B) IRPC parameter,string ex: irpc xx,12345 db '&xx' endm is exanded as: 0009: 31 db 1 000a: 32 db 2 000b: 33 db 3 000c: 34 db 4 000d: 35 db 5 C) Conditional Assembly ----------------------- ifidn <'a'>,<'a'> ;'a'=61hex 'b'=62hex db 'a=a' else db 'a!=a' endif ifidn <'a'>,<'b'> ;'a'=61hex 'b'=62hex db 'a=b' else db 'a!=b' endif is expanded as: 0003: 61 3d 61 db 'a=a' 0006: 61 21 3d 62 db 'a!=b' ifidn <aa>,<bb> ;aa and bb are VARIABLE not ARGUMENT ! ;compile if aa==bb db endif irpc xx,<string> Loop in macro: -------------- liason C-ASM: ------------- PArg1 equ byte ptr 4[bp] PArg2 equ word ptr 6[bp] PbLoc1 equ byte ptr -2[bp] PiLoc2 equ word ptr -3[bp] PbLoc3 equ byte ptr -4[bp] push bp mov bp,sp sub sp,10 ;reserve 10 byte for local variable push bx push cx push es push di Stack: Argn bp+4+n*2 .. Arguments Arg1 bp+4 ip bp+2 bp bp+0 loc1 bp-2 loc2 Local variables .. bx register cx es si mov ax,PArg1 ;->warning mov es,PArg2 ;->possible due to word ptr pop di pop es pop cx pop bx add sp,10 pop bp ret Bibliography: IAPX 86-186 User's Manuel p 3-39 80x86 Clock notation Microprocessors Volume I 1991 p 2-26..2-30 8086 Instruction Set Summary p 2-85..2-89 8088 Instruction Set Summary p 3-49..3-59 80C286 Instruction Set Summary p 3-66..3-68 80286 Instruction Set Overview p 3-68..3-70 80286 Addressing mode p 3-105..3-115 80286 Instruction Set Summary p 5-380..5-394 80386DX Instruction Set Clock Count Summary p 5-889 80386SX Segment descriptor p 5-890 80386SX Code & Data descriptor p 5-891 80386SX System descriptor p 5-939..5-953 80386SX Instruction Set Clock Count Summary Microprocessors Volume I 1992 p 2-146..2-164 80486DX Microprocessor Integer Clock Count Summary Microprocessors Volume II 1993 p 6-106..6-115 80286 Instruction Set Summary p 6-49..6-6-59 80C286 Instruction Set Summary p 5-550..5-564 80386SX Instruction Set Clock Count Summary p 5-94..5-108 80386DX Instruction Set Clock Count Summary Microprocessors Volume I 1993 p 2-152..2-165 Intel486 DX2 Microprocessor Interger Core clock summay Microsoft Macro Assemblor 5.1: Programmer's guide p 135 DUP p 145 [name] structurename<[initialvalue,[initialvalue]]> p 148 recordname RECORD field [,field...] p 205 .ERR p 214 redifinable = p 215 non redifinable EQU expression p 216 non redifinable EQU <string> p 222 EXITM p 223 REPT p 224 IRP p 225 IRPC